<p><strong><span data-contrast="auto">About Graphcore</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <p>At Graphcore, we’re building the future of AI compute.</p> <p>We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.</p> <p>As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.</p> <p>To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.</p> <p>We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.</p> <p><strong><span data-contrast="auto">Job Summary</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">We are seeking a Director of Silicon Logical Design to lead and scale our Logical Design&nbsp;group&nbsp;within the Silicon department. This role is accountable for the overall strategy, technical direction, execution&nbsp;quality&nbsp;and team development for&nbsp;Graphcores&nbsp;microarchitecture and RTL design efforts.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">The Director will&nbsp;be responsible for&nbsp;ensuring that our logical design methodologies,&nbsp;architectures&nbsp;and RTL implementations meet world&nbsp;class standards for performance, power, area, and schedule. This leader will partner closely with Architecture, Physical Design, Verification, DFT and Program Management&nbsp;teams&nbsp;to ensure successful, predictable silicon delivery aligned with&nbsp;Graphcores&nbsp;long&nbsp;term product roadmap.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><strong><span data-contrast="auto">The Team</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">The Logical Design team deliver the micro-architecture and RTL that realise our advanced chip architectures. As Director, you will guide this multi site team, strengthen cross functional collaboration, and drive the evolution of our design flows and capabilities.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><strong><span data-contrast="auto">Responsibilities and Duties</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <p><em><span data-contrast="auto">Leadership &amp; Strategy</span></em><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="0" data-aria-level="1"><span data-contrast="auto">Define and execute the strategic roadmap for Logical Design, ensuring alignment with&nbsp;Graphcores&nbsp;silicon and product strategy.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Lead, grow and mentor a high&nbsp;performing&nbsp;RTL/micro&nbsp;architecture design organisation.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Establish&nbsp;and implement&nbsp;best&nbsp;in&nbsp;class design methodologies, documentation&nbsp;standards&nbsp;and quality metrics.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Drive continuous improvement across team structure, workflows, tooling, and design processes.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p>&nbsp;</p> <p><em><span data-contrast="auto">Technical Ownership</span></em><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Provide technical oversight of micro&nbsp;architecture specification and RTL development across all major blocks and subsystems.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Guide architectural feasibility studies, contribute to architectural&nbsp;trade&nbsp;offs&nbsp;and micro&nbsp;architecture definition.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Oversee the integration of&nbsp;third&nbsp;party&nbsp;IP, complex application&nbsp;specific blocks, and&nbsp;high&nbsp;performance&nbsp;custom designs.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Ensure robust design sign&nbsp;off through high&nbsp;quality linting, synthesis, CDC/RDC, timing closure and coverage metrics.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><span data-ccp-props="{}">&nbsp;</span></p> <p><em><span data-contrast="auto">Cross-Functional Collaboration</span></em><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto">Partner closely with Physical Design, Verification, DFT, Architecture and Program Management&nbsp;teams&nbsp;to ensure cohesive planning and execution.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="9" data-aria-level="1"><span data-contrast="auto">Foster&nbsp;strong communication&nbsp;across teams and global sites, ensuring alignment on priorities,&nbsp;risks&nbsp;and deliverables.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="10" data-aria-level="1"><span data-contrast="auto">Support silicon bring-up and debug efforts by providing expert guidance and deep understanding of RTL behaviour and architecture.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><span data-ccp-props="{}">&nbsp;</span></p> <p><em><span data-contrast="auto">Execution &amp; Delivery</span></em><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="11" data-aria-level="1"><span data-contrast="auto">Own delivery of high&nbsp;quality, on&nbsp;schedule RTL for multiple&nbsp;parallel&nbsp;silicon programs.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="12" data-aria-level="1"><span data-contrast="auto">Establish scalable project planning and tracking practices, including resource planning and risk mitigation.</span><span data-ccp-props="{}">&nbsp;</span></li> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="13" data-aria-level="1"><span data-contrast="auto">Champion design automation and infrastructure improvements to accelerate productivity and improve design quality.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><strong><span data-contrast="auto">Essential Skills &amp; Experience</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="14" data-aria-level="1"><span data-contrast="auto">Degree in Computer Science, Electrical&nbsp;Engineering&nbsp;or a related field; advanced degree preferred.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="15" data-aria-level="1"><span data-contrast="auto">Extensive experience in digital logical design, micro-architecture and RTL development for large scale, high performance silicon projects.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="16" data-aria-level="1"><span data-contrast="auto">Proven success leading and developing technical teams in a semiconductor environment.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:1440,&quot;335559991&quot;:720,&quot;469769226&quot;:&quot;Aptos&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;•&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="17" data-aria-level="1"><span data-contrast="auto">Deep&nbsp;expertise&nbsp;in&nbsp;SystemVerilog&nbsp;or VHDL and familiarity with modern digital design flows.</span><span data-ccp-props="{}">&nbsp;</span></li> &l